TDM over IP

IPM-E1/4E1 is designed as a multi-service access platform for PDH over IP applications. E1 frames can be mapped/de-mapped into/ from IP packets. An adaptive clock recovery method for Ingress PDH (PSN->TDM) clock generation is implemented to support E1 (ITU-T G.823) Jitter performance.

• Supports Web Management
• Supports IETF RFC4553 Structure-Agnostic TDM over Packet (SAToP), Metro Ethernet Forum MEF8
• Use Raw Encapsulation method for PDH payload over Ethernet packet
• Supports Circuit Emulation Service over Ethernet networks
• Comply with IETF draft standard for CESoPSN and SAToP; Metro Ethernet Forum MEF8 IA
• Supports both Point-to-Point and Point-to-Multipoint operation
• Supports Adaptive Clock recovery block for Ingress PDH (PSN -> TDM) clock generation. Recovered clock jitter is compliant to ITU-T G.823 (E1 Jitter Control)
• Configurable jitter buffer depth to compensate PDV (Packet Delay Variation) with the flexible setting of 11ms, 23ms, 40ms, 75 ms
• Lost packets processing / compensation via PW (Pseudo Wire) control field Sequence Number
• Provide Subscriber side Data traffic bandwidth control to guarantee enough TDM payload bandwidth
• PDH LOS detection triggered PW L field or payload AIS generation at Egress direction (TDM->PSN)
• Configurable IEEE 802.3 DA/SA assignment
• LED alarm display for E1 Power failure status
• E1 NRZ Serial Interface with LOS/AIS detection

IPM-8E1 & IPM-16E1 is designed as a multi-service access platform for PDH over IP applications. E1 frames can be mapped/de-mapped into/from IP packets.

• Supports Web Management
• Supports IETF RFC4553 Structure-Agnostic TDM over Packet (SAToP), Metro Ethernet Forum MEF8
• 8 /16 x E1 NRZ Serial Interface with LOS/AIS detection
• Use Raw Encapsulation method for PDH payload over IP packet
• Supports Circuit Emulation Service over IPE
• Comply with IETF draft standard for CESoPSN and SAToP; Metro Ethernet Forum MEF8 IA
• Supports both Point-to-Point and Point-to-Multipoint operation
• Configurable IEEE 802.3 DA/SA assignment
• Supports 8/16 independent Adaptive Clock recovery block for Ingress PDH (PSN->TDM) clock generation. Recovered clock jitter is compliant with ITU-T G.823 (E1 Jitter Control)v
• Independent configurable jitter buffer depth to compensate up to 250ms of Packet Delay Variation
• Lost packets processing / compensation via PW (Pseudo Wire) control field Sequence Number
• PDH LOS detection triggered PW L field or payload AIS generation at Egress direction (TDM->PSN)
• LED alarm display for E1 Power failure status